1. Field of the Invention
The present invention generally relates to high density memory modules for computers and, more particularly, to multiple bank memory modules having minimal memory bus loading.
2. Background Description
High density memory modules, e.g., single in-line memory modules (SIMMS) and dual in-line memory modules (DIMMs), continue to be in demand for high end personal computers (PCS), network servers and workstations, as added system performance can be achieved in many applications. However, the maximum system density often is artificially limited by one or more of the following:
The system has a limited number of memory module "slots". PA0 The system has a limited number of memory "banks" (due to a lack of select lines from the memory controller). PA0 High density memory chips (e.g., 64 megabit (Mb), 256 Mb and greater) are either very expensive and/or not readily available. PA0 High density memory chips may have an operating voltage which is lower than the system memory interface voltage. PA0 The use of stacking/cubing or oversize modules (with standard random access memory (RAMs) devices including dynamic RAMs (DRAMs), synchronous DRAMs (SDRAMs) and static RAMs (SRAMs)) results in a data line capacitance well beyond system limits.
Previous solutions have been provided for all but the last of the above problems, but these solutions have been limited in applicability due to data line loading concerns. What is needed in order to better utilize less expensive RAM chips in systems with otherwise limited memory expansion is a way to minimize data line capacitance loading so that oversize memory modules with banks of RAM chips can be added to the system.